The failure characteristic of a semiconductor device is an important specification for customers of the semiconductor device. The failure characteristic typically includes an expected life-time of the semiconductor device. For determining such a failure characteristic, the semiconductor device is stressed with application of stress bias voltages.
FIG. 1 shows a MOSFET (metal oxide semiconductor field effect transistor) 100 as the semiconductor device that is a common component of integrated circuits. The MOSFET 100 includes a drain 102, a source 104, a gate dielectric 106, and a gate structure 108 formed within an active device area 110 of the semiconductor substrate 112. The active device area 110 is surrounded by STI (shallow trench isolation) structures 114.
One prior art method of determining the failure characteristic of the MOSFET 100 is termed the HCI (hot carrier injection) stress method. For the HCI stress method, a drain to source voltage VDS 116 is applied across the drain 102 and the source 104 of the MOSFET 100. In addition, a gate to source voltage VGS 118 is applied across the gate structure 108 and the source 104 of the MOSFET 100.
FIG. 2 shows a plot 120 of drain current IDS versus the drain to source voltage VDS for the MOSFET 100. At a snap back voltage VDS—sb 122, the drain current begins to ramp up more sharply as the MOSFET 100 is no longer in saturation. The drain to source voltage VDS for the HCI stress method is typically required to be less than the snap back voltage VDS—sb 122.
FIG. 3 shows a plot 124 of the substrate current Isub (i.e., the current flowing through the substrate 112 in FIG. 1) versus the gate to source voltage VGS for the MOSFET 100. The substrate current Isub peaks at a peak gate voltage VGpeak 126. For maximizing voltage stress on the MOSFET 100 in the HCI stress method, the gate to source voltage VGS is set at the peak gate voltage VGpeak. Typically, VGpeak≈½VDS—sb.
In the HCI stress method, the MOSFET 100 is stressed with the drain to source voltage VDS 116 being set to be less than the snap back voltage VDS—sb 122 and with the gate to source voltage VGS 118 being set at the peak gate voltage VGpeak 126. After such voltage stress for various time periods, device characteristics of the MOSFET 100 are measured for determining the failure characteristic of the MOSFET 100.
In some applications, the MOSFET 100 may need to operate at relatively high voltages such as 9–12 Volts and at relatively high temperatures such as 150° Celsius or above for example. For such operating conditions, the HCI stress method cannot be used when the snap back voltage VDS—sb 122 for the typical MOSFET is about 7–8 Volts.
The TDDB (time dependent dielectric breakdown) method is another prior art technique for determining the failure characteristic of the semiconductor device such as the MOSFET 100. However, the TDDB method uses capacitor structures for characterizing the quality of the gate dielectric of a MOSFET and is limited in qualifying other characteristics of the MOSFET.
Thus, an accurate failure characterization process is desired for a wide range of device operating conditions including higher operating voltages such as 9–12 Volts and higher temperatures such as 150° Celsius or above, for example.